[CONTRACT] ASIC Design & Verification Engineer > Joboolo BE :
Société : microTECH Global Ltd Lieu : Flemish Brabant Flanders Site source : Talent BE
for further design and flow improvementsRequired Experience - Solid grasp of simulation concepts such as regression testing, UVM, functional coverage, assertions, … - Good knowledge of Verilog and SystemVerilog for design and verification - Experience with RTL lint - Knowledgeable about DFT and ATPG - Knowledgeable about CDC issues and techniques for low power design - Experience with delay annotated gatelevel simulation - Experience with implementation of high-speed pipelined FIR DSP structures is a plus - Formal Verification experience is a plus - Formal lint - Sequential Equivalence Checking - Assertion Based Verification - Experience with C/C++/SystemC models for RTL verification a must - Python and TCL programming experience a strong plus - Able to efficiently work in a Linux command line environment as well as in Windows MS Office for reporting and documentation microTECHGlobal Ltd FlemishBrabantFlanders
